04-005: Double-Gated SOl Ratioed Logic with "Intrinsically On" Symmetric DG-MOSFET Load

As scaling of circuits continues deep into sub 90 nm it has become harder to fabricate without compromising performance and increasing cost. This DG fully depleted SOl MOSFET is an ideal technological choice for cutting edge nano-scale circuits.

- Predictable and controllable manufacturing costs.
Existing simple dual poly (n+/p+) process is required to fabricate these gates.
- Increased functionality and improved performance.
Near-ideal intrinsic features, small size, and small parasitic capacitance.
- Pseudo-nMOS/ratioed logic on SOl may be used in SOl custom-integrated circuits.
- Faster response characteristics at higher frequencies than equivalent CMOS devices.
- Devices may be constructed to dissipate less power than equivalent CMOS devices.
- Complex multi-input gates may be constructed with fewer devices and without performance penalties.
- Takes advantage of the "normally on" state of an SDG gate.


Double-Gated Silicon-On-Insulator (SOl) Metal-Oxide Semiconductor Field-Effect Transistors (MOSFET) are thought to be the most viable candidate in overcoming the scaling limits of bulk CMOS technology down to channe1lenghts of 50nm or less. This invention is a SOl MOSFET logic family, composed of ratioed logic with intrinsically "on" symmetric fully depleted double-gate (DG) SOl MOSFET load(s) and asymmetric fully depleted double gate MOSFET driver(s). These logic gates use a basic Pseudo-nMOS logic design, in which both PMOS and NMOS transistors are combined to produce logic elements. Certain parameters, such as noise margin, threshold voltage, and load current characteristics vs. output voltage make these gates more robust and a better design than conventional CMOS gates. So far, the logic family includes an inverter, a NAND gate, a NOR gate, two NAND gates, and an XOR gate.