01-037: Hardware IP Cores of Advanced Encryption Standard

Advanced Encryption Standard hardware cores developed by Dr. Kris Gaj at George Mason University implement the Rijndael encryption/decryption algorithms chosen as the new standard by the National Institutes of Standard (NIST).

The cores are based on a fully synthesizable RTL VHDL code and have been optimized for implementation in ASIC and FPGA chips. In addition to the Advanced Encryption Standard cores Dr. Gaj has developed hardware cores for Triple DES, MARS, RC6, Twofish, and Serpent. All cores offer similar interfaces and have been optimized for use with both FPGA and ASIC devices.

AES Features:
- Three architectures - iterative, inner-round pipelined, and fully pipelined
- Supports key sizes up to 256k without incurring speed penalty
- Encryption and decryption in same device without incurring speed penalty
- CBC and ECB modes of operation implemented by default and easily extended to other modes
- Key scheduling performed in parallel with encryption and decryption
- Very high encryption and decryption throughputs in excess of 17 Gbits
- Efficient use of circuit area
- Simple and universal external interface
- Customized separation between encryption and decryption

Market Significance:

For use in any application that requires protection of data during transmission through communication networks
- Electronic commerce transactions
- ATM Machines
- Wireless Communications
- Virtual Private Networks
- Hardware implementation of all major security protocols, including IP SEC, SSL, IEEE

802.IIa, and ATM Security Specification